1. Field of the Invention
The invention pertains to the semiconductor field. More particularly, the present invention relates to an apparatus and a parallel test mode method for verifying the functionality of memory cells in a memory device.
2. Description of the Related Art
As the density of memory devices increases, so does the time and expense of testing the functionality of each memory cell contained therein. For example, to completely test a 256K.times.18 memory device, namely a device having about 256,000 memory locations, each location consisting of 18 memory cells, takes about 256,000 cycles. Each such cycle consists of writing a data bit (a 1 or a 0) to each of the 18 memory cells, and insuring that the data bit thereafter read from each of the 18 memory cells is identical to the data bit that was written thereto.
In an effort to reduce the testing time of such memory devices and the expense associated therewith, memory devices have been developed that incorporate parallel test mode circuitry to allow, for example, .times.1 and .times.4 organizations to be tested as a .times.8 organization, or a .times.16 organization to be tested as a .times.32 organization. The ".times.n" nomenclature refers to the number of I/O data pins on the device, where n is the number of I/O data pins. Conventional test mode schemes, however, are limited in the number of bits that may be simultaneously tested, and/or require that expected data be provided as an input to the memory device during the read portion of each testing cycle. Moreover, such schemes are typically limited in the number of bits that may be tested during any given cycle to the number of sets of data lines and global sense amplifiers within the device. Alternatively, such schemes may require additional circuits in the data line, such as a multiplexer, to select more than one data line during the test mode of operation. Such additional circuits, however, if not required during the normal operation of the memory device, often detrimentally add to the overall access time of the device.
What is needed, therefore, is an apparatus and a method for carrying out parallel testing of memory devices, in which the number of memory cells that may be simultaneously tested is not limited to the number of sets of data lines in the device. What is also needed is an apparatus for carrying out parallel testing of memory devices in which it is not necessary to provide expected data to the device, or to provide a separate I/O pin for the expected data. What is also needed is an apparatus for parallel testing memory devices that does not rely upon access time degrading circuitry in the data line to carry out the testing procedure.